High voltage devices, such as high voltage field-effect transistors, having high breakdown voltage and low on-state resistance are used in integrated circuits (ICs) for high voltage applications. Such high voltage field-effect transistors include lateral double-diffused metal oxide semiconductor (LDMOS) transistors. In some high voltage applications, an integrated circuit may include multiple LDMOS transistors connected in parallel to allow higher current handling capabilities. This requires individual LDMOS transistors to be uniformly formed so as to ensure even distribution of current among each of the transistors. However, conventional processes for forming LDMOS transistors are difficult to control and unreliable in forming uniform LDMOS transistor gates.
Moreover, the performance of an LDMOS transistor generally depends on the drain-to-source on-resistance (Rdson) as well as breakdown voltage (Vbr). For high performance LDMOS transistors, low drain-to-source on-resistance (Rdson) is desired to minimize its power dissipation when it is turned on, as well as high Vbr to maximize its voltage capability. For example, lower Rdson results in higher switching speeds while higher Vbr increases device reliability. Generally, higher breakdown voltage may be achieved by increasing the drain-to-gate surface area on the substrate. This however increases gate-to-drain capacitance, resulting in a larger Rdson. Thus, there is often a trade-off between Rdson and Vbr during performance optimizations.
Accordingly, there is a need to provide improved high voltage devices that have lower Rdson as well as higher Vbr. In addition, there is also a desire to provide precise and reliable methods to form these high voltage devices.